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ADE7518
POWER MANAGEMENT
The ADE7518 has elaborate power management circuitry that manages the regular power supply to battery switchover and power supply
failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 14).
Table 14. Power Management SFRs
SFR Address
0xEC
0xF5
0xF8
0xFF
0xF4
0xC5
0xFB
0xFC
0xFD
0xFE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mnemonic
IPSME
BATPR
IPSMF
INTPR
PERIPH
POWCON
SCRATCH1
SCRATCH2
SCRATCH3
SCRATCH4
Description
Power Management Interrupt Enable. See Table 19.
Battery Switchover Configuration. See Table 17.
Power Management Interrupt Flag. See Table 16.
Interrupt Pins Configuration. See Table 15.
Peripheral Configuration SFR. See Table 18.
Power Control. See Table 24.
Scratch Pad 1. See Table 20.
Scratch Pad 2. See Table 21.
Scratch Pad 3. See Table 22.
Scratch Pad 4. See Table 23.
POWER MANAGEMENT REGISTER DETAILS
Table 15. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit
7
Mnemonic
RTCCAL
Default
0
Description
Controls the RTC calibration output. When this bit is set, the RTC calibration frequency selected by
FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin.
6 to 5
FSEL[1:0]
00
Sets the RTC calibration output frequency and calibration window.
FSEL[1:0] Result (Calibration Window, Frequency)
00
01
10
11
30.5 sec, 1 Hz
30.5 sec, 512 Hz
0.244 sec, 500 Hz
0.244 sec, 16.384 kHz
4
Reserved
N/A
3 to 1
0
INT1PRG[2:0]
INT0PRG
000
0
Controls the function of INT1.
INT1PRG[2:0]
Result
x00
GPIO enabled
x01
BCTRL enabled
01x
INT1 input disabled
11x
INT1 input enabled
Controls the function of INT0.
INT0PRG
Result
0
INT0 input disabled
1
INT0 input enabled
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the Key SFR (KYREG, 0xC1) to obtain write access to INTPR. KYREG
(see Table 105) should be set to 0xEA to unlock this SFR and then reset to zero after a timekeeping register is written to. The RTC
registers can be written using the following 8052 assembly code:
MOV
MOV
KYREG, #0EAh
INTPR, #080h
Rev. 0 | Page 22 of 128
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